Rev F and earlier 5386 hardware use an external Watch Dog chip that resets the 386 processor and the DSP in case the 386 processor locks up.

Rev F and earlier 5386 hardware has a signal line P1.3 that resets the DSP, which makes the IO on the 5387 board safe in cases where a Task Error or some other unsafe condition is detected by the software.

On Rev H hardware, resetting the ARM, to make the IO safe during a task error will also reset the 386, which is undesirable.

So here are the changes.

1. P1.3, which is connected to the ~MR line will now be monitored by the ARM. The Watch Dog Chip is also connected to this line. The 386 can either drive this pin low or let the Watch Dog Chip do it to reset the system. .
2. The 386 will rely on the ARM to make the IO safe if the 386 fails to send the cyclical IO data to it. On a system reset the ARM will NOT have any IO ON or configured. The IO states are contained within the cyclical data. Once the cyclical data starts being received, if the ARM then fails to receive the expected data it will go into a safe mode and reset the 5387 board to make the IO safe.
3. Undo, SCN 4290 which removed the Watch Dog operation for Rev G boards.
4. While programming the Boot with the Universal Programmer the ~MR line is driven low. Unless the ARM knows that the Universal Programmer is being used, it will reset the 386 and thwart the programming. The ARM is able to indirectly monitor the FWP line that is driven low by the JTAG connector from the Universal Programmer. The Keyboard Pic drives this line low to signal Flash Programming mode desired. The Keyboard Pic is now placed in reset when entering Flash Program mode so that it will release the FWP line. This may be unnecessary since the Watch Dog is disabled during Flash Programming Mode but it makes the operation of the FWP line consistent between entering Flash Program mode via the Keypad or through the debug P command.

Notes!!!! In order to make the WatchDog system and code work the same way as the Ref F board it would be preferable for the ARM to be able to hold the ~MR line low while the reset occurs. The Watch Dog Chip has special logic to continue holding the line low for 100msec after it is released externally. The ARM would wait for the Watch Dog to release the line before bringing the 386 out of reset. This would synchronize the Watch Dog and 386, preventing the 386 from trying to talk to the Watch Dog until it is ready to accept communication. It would also prevent the watch dog from running before the 386 is ready keep the Watch Dog happy. It would make the Watch Dog effectively reset the system the same way as the Ref F where the 386 would start after the 100msec low enforced by the WatchDog. Since we can't do that, it appears as if the Boot16 code attempts to stop the watch dog nearly as soon as it boots. It is able to see if the Watch Dog is responding and retries many times if it doesn't. The worst that will happen is that the ARM will reboot the system again if the Watch Dog fails