External Memory and other devices must provide a ready signal to the 80386 processor when the processor attempts to read or write them. Unless interrupted, the processor will wait forever if a ready signal is not given.

In order to detect hardware or software conditions that cause this the Rev H 5386 board has a CPLD chip with logic to detect the error and trigger an interrupt. The interrupt is IRQ 9.

When IRQ 9 occurs the controller will display a Task Error 8F00xxxx where xxxx is the status register from the CPLD that contains information that will help engineering determine which device or software is responsible for the timeout.