Changes made for Pathfinder 5226 controllers.

The change: one line, the clock divider.

// Rev F (25 MHz): assign CLK = CNT[1]; // ÷4 ? 6.25 MHz internal

// Rev H (12 MHz): assign CLK = CNT[0]; // ÷2 ? 6.0 MHz internal Why: The SSI clock is CLK25 / 256. At 12 MHz the ÷4 divider gave a 46.9 kHz SSI clock (~21 µs period), which exceeds the encoder's monoflop timeout ? the encoder resets mid-frame ? jumpy low bits + error bit. Switching ÷4 ? ÷2 makes 12 MHz ÷ 2 = 6.0 MHz ˜ the original 25 MHz ÷ 4 = 6.25 MHz, restoring the SSI clock to ~94 kHz (~10.7 µs period), back under the monoflop.

Effect: Everything derived from CLK (SSI clock, monoflop window, update rate, incremental filter) returns to the proven rev-F timing. No other lines change. Rev H bitstream only — recompile/reflash; rev F unchanged.